Setup

Quickstart for building, simulating, and synthesizing riscv-5i. Tested on Ubuntu 22.04 and Fedora; other Linux distros should work with equivalent package names.

Dependencies

The repo needs an open-source HDL toolchain (Icarus Verilog, GTKWave), a RISC-V GCC cross-compiler, RISCOF, and Xilinx Vivado for the FPGA path.

sudo apt-get update
sudo apt-get install -y iverilog gtkwave python3 python3-pip git
sudo apt-get install gcc-riscv64-unknown-elf
pip3 install riscof

Vivado is a separate install from Xilinx (free WebPACK edition is enough for the Zynq-7000 target). Tested with Vivado 2025.2.

Clone and bootstrap

git clone https://github.com/cshieldsce/riscv-5i.git
cd riscv-5i
./setup_project.sh

setup_project.sh clones the RISC-V architectural test suite into test/verification/riscv-arch-test/ and verifies that riscv64-unknown-elf-gcc is on your PATH.

Sanity check:

iverilog -v
riscv64-unknown-elf-gcc --version
riscof --version
ls test/verification/riscv-arch-test/

Simulation

A single test, with a memory image:

cd test/tb
iverilog -g2012 -I ../../src/ -o sim.out \
    ../../src/riscv_pkg.sv \
    ../../src/*.sv \
    pipelined_cpu_tb.sv
vvp sim.out +TEST=../mem/fib_test.mem
gtkwave waveform.vcd

The +TEST= plus-arg points at a .mem initialization file under test/mem/. Drop in any RV32I program assembled to that format and the testbench runs it through the pipeline; the VCD writes to waveform.vcd for GTKWave.

To compile and run from the repo root instead of test/tb:

iverilog -g2012 -o sim.out -I src/ src/pipelined_cpu.sv test/tb/pipelined_cpu_tb.sv
vvp sim.out +TEST=test/mem/fib_test.mem

Compliance run

The full RISCOF suite against Spike runs end-to-end in one script:

./test/verification/run_compliance.sh

The HTML report lands in test/verification/riscof_work/report.html. Plugins for the DUT and golden model live under test/verification/compliance/ if you want to swap out targets.

FPGA build

The Vivado project is generated by a TCL script that lives under fpga/:

cd fpga
vivado -mode batch -source create_project.tcl

From there, synthesize, implement, and program the board through the Vivado GUI or its TCL prompt. The PYNQ-Z2 top-level wiring (LEDs, clock, reset) lives in src/pynq_z2_top.sv; the synthesis and timing results are on the FPGA page.